This invention relates to digital signal processing (DSP) circuitry. More particularly, this invention relates to providing a flexible accumulator in DSP circuitry.
A programmable logic resource is a general-purpose integrated circuit that is programmable to perform any of a wide range of logic tasks. Known examples of programmable logic resource technology include programmable logic devices (PLDs), complex programmable logic devices (CPLDs), erasable programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), and field programmable gate arrays (FPGAs).
Manufacturers of programmable logic resources, such as Altera® Corporation of San Jose, Calif., have recently begun manufacturing programmable logic resources that, in addition to programmable logic circuitry, also include hardware DSP circuitry in the form of multiplier-accumulator (MAC) blocks. The MAC blocks of programmable logic resources provide a way in which certain functionality of a user's design may be implemented using less space on the programmable logic resource, thus resulting in a faster execution time because of the nature of DSP circuitry relative to programmable logic circuitry. MAC blocks may be used in the processing of many different types of applications, including graphics applications, networking applications, communications applications, as well as many other types of applications.
MAC blocks are made of a number of multipliers, accumulators, and adders. The accumulators can perform add, subtract, or accumulate operations. Typically, there are four multipliers, two accumulators, and an adder in a MAC block. The MAC block can have a plurality of modes which may be selectable to provide different modes of operation.
During one mode of operation, the MAC block can implement multiply-and-accumulate operations. During this mode of operation, each accumulator adds or subtracts the output of a multiplier from an accumulator value. The accumulator value can be a value previously computed by the accumulator and stored in an output register. In known MAC blocks, the accumulator value can be zeroed by setting a control signal to clear the output register. In addition, known MAC blocks do not allow for the accumulator value to be initialized to a non-zero value with minimum clock latency.
In view of the foregoing, it would be desirable to provide a MAC block that can zero an accumulator value without introducing clock latency and that can also initialize the accumulator value with minimum clock latency.